1. Technical Field
The present invention relates to a CMOS output buffer protection circuit and, more particularly, to a CMOS output buffer protection circuit formed in low voltage CMOS technology (i.e. 3.3V) that is tolerant of high input voltages (i.e. 5V).
2. Description of the Prior Art
In many areas of CMOS circuit design there are arrangements that include sections that run between 0-5V and other sections that use a voltage supply range of only 0-3.3V. There is often a need to provide a "buffer" circuit between these sections. Thus, there is a need to supply a circuit in standard low voltage CMOS technology (e.g., 3.3V) that can tolerate a relative high voltage (i.e., 5V) on its input. Additionally, many system configurations require a circuit that is "hot pluggable", meaning that the circuit will not draw any current from a bus that is at a high voltage, even when the circuit is not powered (i.e., when VDD is not present). Further, the circuit should be designed so that it is not "harmed" when exposed to relatively high voltages. In particular, if the gate oxide of a MOS transistor is subjected to too high a voltage, it will break down, causing gate-to-drain and/or gate-to-source shorts. Likewise, the drain-to-source junction of a MOS transistor will be degraded by hot carriers if it is subjected to too great a voltage. Thus, a MOS circuit that is subjected to voltages higher than the technology is designed to work at must be designed in such a way that the individual transistors in the circuit never see these higher voltages across their gate oxides or their source-to-drain junctions.
One problem with a low voltage technology CMOS buffer interfacing with a relatively high voltage is that the source of a P-channel output transistor is usually connected to the low voltage power supply VDD. If a voltage greater than VDD is applied to the drain of this device (where the drain is usually connected to the PAD of the buffer), it will forward bias the parasitic diode inherent in the P-channel device, since the N-tub backgate of the P-channel transistors is usually connected to VDD.
The prior art circuit of FIG. 1 solves this problem by generating a supply voltage VFLT that is equal to VDD when the PAD voltage is less than VDD, and that is equal to the PAD voltage when PAD is greater than VDD. This reference voltage VFLT is then applied to the N-tub backgate of all P-channel transistors whose source or drain is connected to PAD voltage. The use of VFLT prevents the parasitic diodes of these transistors from ever being forward biased. Referring to FIG. 1, voltage generator circuit 10 is configured to generate a supply voltage VFLT that may be applied to the N-tub backgate of a pair of P-channel transistors 10 and 12. As configured, circuit 10 is used for situations where the PAD voltage (signal bus) appearing at node A may be (at times) greater than the supply voltage VDD. In particular, when PAD goes higher than VDD by a single P-channel threshold voltage, denoted Vtp, transistor 12 turns "on" and transistor 10 turns "off". The output voltage, VFLT, is then equal to the PAD voltage. Therefore, the backgate voltage will be brought up to the high level of PAD and prevent the turn "on" of its associated parasitic diode. During normal operating conditions when PAD&lt;VDD, transistor 10 will be "on" and transistor 12 will be "off", allowing output voltage VFLT to be equal to VDD. While this design affords some protection for high voltages appearing at the PAD terminal, it is not "hot pluggable". That is, if VDD is not present, circuit 10 as depicted in FIG. 1 will have the full PAD voltage across the gate oxide of transistor 10. If this PAD is a relatively high voltage, then the reliability of the circuit is at risk.
One known solution to the above criteria is to utilize a relatively thick gate oxide for any devices that may be exposed to the relatively high voltages at their gate terminals and utilize a standard gate oxide for all remaining devices. This is a very expensive technique that adds appreciable extra cost and process time to conventional CMOS processing technology.